When depositing for instance III-N epitaxial layers on Si substrates, growth is started with the deposition of an AlN layer to suppress the so-called “Ga melt-back” of the Si substrates. At the interface between the Si and the AlN, a conductive layer is formed, due to either the band alignment at the interface or in-diffusion of Ga into the Si. This conductive layer is detrimental for both RF and high voltage operation of devices constructed on top of such III-N buffers on Si.
In case of RF devices, RF signals may couple capacitively with this layer which leads to undesired losses in the propagating signal.
In case of high voltage devices with sufficiently high contact spacing, the device will prematurely break down under high field conditions through a path made up of two vertical legs going, from contact to the III-N/Si interface and the conductive path at the III-N/Si interface itself. In other words, it has been observed that AlGaN/GaN HEMT devices on silicon have a saturated breakdown voltage, even if a distance between the source and the drain region was large. The level of the breakdown saturation is a function of the total thickness of the epitaxial layer stack, so high breakdown voltages require thick epitaxial layers which may result in large wafer bow or cracked layers and which increases the cost of the wafer. Document CN 101719465 (A) provides a method for manufacturing a silicon substrate GaN-based semiconductor material, aiming at solving the problem of re-melting a silicon surface by Ga in the process of extending GaN-based semiconductor material to improve the quality of the product and the production efficiency. The method comprises the following steps of: generating an aluminum nitride buffer layer on the silicon substrate in a reaction chamber of a first MOCVD specially for growing the aluminum nitride buffer layer, and taking out the aluminum nitride buffer layer after the step is completed to form a silicon substrate aluminum nitride template for later use; and placing the silicon substrate aluminum nitride template for later use into a reactor of a second MOCVD for growing a GaN-based semiconductor material to extend the GaN-based semiconductor material; and taking out the silicon substrate aluminum nitride template after the step is completed to form a silicon substrate GaN-based semiconductor material. The method can be applied to production manufacture of light-emitting diodes, diode lasers, power devices and the like.
Umeda, et al. propose in “Blocking-Voltage Boosting Technology for GaN Transistors by Widening Depletion Layer in Si Substrates” (2010 IEEE Electron Devices Meeting, San Francisco, Calif., pages 20.5.1-20.5.4) a novel technique to boost the blocking voltage of AlGaN/GaN hetero junction field effect transistors (HFETs) by widening a depletion layer in highly resistive Si substrate. The blocking-voltage boosting (BVB) technology utilizes ion implantation at the peripheral area of the chip as channel stoppers to terminate the leakage current from the interfacial inversion layers at AlN/Si. A depletion layer is widened in the substrate by the help of the channel stopper, which increases the blocking voltage of the HFET. The off-state breakdown voltage of the HFETs is increased up to 1340V by the BVB technology from 760V without the channel stoppers for the epitaxial GaN as thin as 1.4 μm on Si. This technology greatly helps to increase the blocking voltage even for thin epitaxial GaN on Si, which leads to further reduction of the fabrication cost.
However, this approach does not necessarily resolve the issue of the breakdown saturation.
Srivastava et al. propose in “Record Breakdown Voltage (2200 V) of GaN DHFETs on Si With 2-μm Buffer Thickness by Local Substrate Removal” (EDL 32-1 2011) a local substrate removal technology (under the source-to-drain region), reminiscent of through-silicon vias and report on the highest ever achieved breakdown voltage (VBD) of AlGaN/GaN/AlGaN double heterostructure FETs on a Si (111) substrate with only 2-μm-thick AlGaN buffer. Before local Si removal, VBD saturates at ˜700 V at a gate—drain distance (LGD)≧8 μm. However, after etching away the substrate locally, they measure a record VBD of 2200 V for the devices with LGD=20 μm. Moreover, from Hall measurements, they conclude that the local substrate removal integration approach has no impact on the 2-D electron gas channel properties.
Disadvantages are that the active device is now located on a very thin membrane which could lead to reliability issues and that the removal of the carrier substrate has negative impact on the thermal resistivity of the layer stack.
In another approach a SOI substrate is used, wherein trenches are etched through the semiconductor substrate to (or through) the buried insulator layer, fully isolating the so-called “source islands” and “drain islands” from the underlying handling wafer.
Disadvantages are that there is always an oxide, which has very high thermal resistance, between the active device and the back side of the substrate through which heat may be dissipated.
Nitronex finally showed that the density of electrons in the parasitic channel may be reduced by nitridation of the Si substrate prior to growth (U.S. Pat. No. 7,247,889) to levels below 1016/cm3, but this does not entirely destroy the conductive channel and hence does not eliminate the breakdown saturation.
Typically the above processes can not be performed in standard CMOS processes, thereby causing extra measures to be taken, if possible at all. Such is not only costly, but may for instance also effect the yield, e.g. because process conditions are not optimal.
US patent application publication No. 2008/0048196 A1 (Strittmatter et al.) is directed to electrical and/or optical component and a process for manufacturing the component, where crystal dislocations in material layers of the component can be reliably avoided by etching one or more trenches into the substrate. The trench is overgrown laterally with at least one semiconductor layer so that the trench is completely covered by the semiconductor layer while forming a gas-filled, especially an air-filled cavity. The component is integrated into the semiconductor layer or in an additional semiconductor layer applied onto the semiconductor layer. The active area of the component is placed, preferably exclusively, above the cavity. To achieve optimal thermal diffusion, the cavity is only slightly wider than the width of the component. For optoelectronic components with an optical wave guide, Strittmatter et al. use the transition from semiconductor to the cavity as a way to optically confine light. If the component is a transistor, Strittmatter et al. replace the substrate by a cavity under the device to eliminate RF loss. In both cases, the cavity needs to have at least the size of the active area of the component and, therefore, of the entire component.